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ISL97636A
Data Sheet May 9, 2008 FN6566.0
6-Channel LED Driver
The ISL97636A is an integrated power LED driver that controls 6 channels of LED current for LCD backlight applications. The ISL97636A is capable of driving typically 54 (6x9) pieces of 3.5V/30mA or 60 (6x10) pieces of 3.2V/20mA LEDs. The ISL97636A's contains 6 channels of voltage controlled current sources with typical currents matching of 1%, which compensate for the non-uniformity effect of forward voltages variance in the LED stacks. To minimize the voltage headroom and power loss in the typical multi-strings operation, the ISL97636A features a dynamic headroom control that monitors the highest LED forward voltage string and uses its feedback signal for output regulation. The LED brightness can be pulse width modulated with an applied PWM signal from DC to audio noise free 20kHz. The ISL97636A features extensive protection functions that include string open and short circuit detections, OVP, OTP, thermal shutdown and an optional input overcurrent protection with master fault disconnect switch. Available in the 24 Ld 4mmx4mm QFN, the ISL97636A operates from -40C to +85C with input voltage ranges from 6V to 24V for high LEDs count applications.
Features
* 6 channels * 6V to 24V Input * 34.5V Output Max * Drive Maximally 54 (3.5V/30mA each) or 60 (3.2V/20mA each) LEDs * Current Matching 1% Typ * Dynamic Headroom Control * PWM Signal up to 20kHz Dimming * Protections - String Open Circuit Detection - String Short Circuit Detection with Selectable Thresholds - Over-Temperature Protection - Overvoltage Protection - Optional Input Overcurrent Protection w/Disconnect SW * 1.2MHz Switching Frequency * 24 Ld 4mmx4mm QFN Package * Pb-Free (RoHS compliant)
Applications
* Notebook Displays LED Backlighting * LCD Monitor LED Backlighting
Ordering Information
PART NUMBER (Note) ISL97636AIRZ* PART MARKING 976 36AIRZ PACKAGE (Pb-free) 24 Ld 4x4 QFN PKG. DWG. # L24.4x4D
* Automotive Displays LED Backlighting * Automotive or Traffic Lighting
*Add "-T" or "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL97636A Typical Application Circuit
VBL+ = 6V TO 24V VOUT = 34.5V, 30mA PER STRING
ISL97636A 21 FAULT 23 VIN 24 VDC LX 19 LX 20 OVP 16 PGND 17 PGND 18
22 COMP
IIN0 15
6 PWMI/EN IIN1 14 11 RSET IIN2 13 IIN3 12 IIN4 10 5 GND IIN5 9
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ISL97636A Block Diagram
VBL+ = 6V TO 24V 34.5V, 30mA PER STRING (6 x 9 = 54 WHITE LEDS)
VIN VDC
FAULT O/P SHORT
LX
REG
FAULT DETECT
OVP FET DRIVER
OSC AND RAMP COMP
=0
IMAX ILIMIT
LOGIC
PGND
COMP
IIN0 GM AMP REFERENCE GENERATOR HIGHEST VF STRING DETECT + OC, SC DETECT
IIN5
OC, SC DETECT FAULT DETECT
RSET GND
+ -
ISL97636A
FAULT DETECT
TEMP SENSOR + PWM/OC/SC
FAULT/DETECT
PWMI/EN
PWM GENERATOR
FIGURE 1. ISL97636A BLOCK DIAGRAM
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ISL97636A
Absolute Maximum Ratings (TA = +25C)
VIN, FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 24V VDC, COMP, RSET, EN/PWM . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V OVP, IIN0 - IIN5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V LX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 36V PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Above voltage ratings are all with respect to GND pin
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) 24 Ld QFN . . . . . . . . . . . . . . . . . . . . . . Thermal Characterization (Typical, Note 3) JA (C/W) 39 JC (C/W) 2 PSIJT (C/W)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C
24 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~0.7 Maximum Continuous Junction Temperature . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside assumed under ideal case temperature. 3. PSIJT is the junction-to-top thermal resistance. If the package top temperature can be measured, with this rating then the die junction temperature can be estimated more accurately than the JC and JC thermal resistance ratings. 4. Limits established by characterization and are not production tested.
Electrical Specifications
All specifications below are tested at TA = -40C to +85C; VIN = 12V, EN = 5V, RSET = 36.6k; Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested DESCRIPTION CONDITION MIN TYP MAX UNIT
PARAMETER GENERAL VIN IVIN_STBY VOUT Vuvlo Vuvlo_hys SS PWM GENERATOR EN/PWM ENmin tMAX_PWM_OFF REGULATOR VDC IVDC_STBY IVDC VLDO BOOST SWILimit
Backlight Supply Voltage VIN Shutdown Current Output Voltage Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis Soft-start
9 LEDs per channel (3.5V/30mA type)
6
24 5 34.5
V A V V mV ms
2.45 300 1
2.8
EN/PWM Voltage Range Minimum Enable Signal Maximum PWMI Off Time Before Shutdown EN/PWMI toggles
2.7 40 28
5.5
V s ms
LDO Output Voltage Standby Current Active Current VDC LDO Dropout Voltage
VIN > 6V EN/PWM = 0V EN/PWM = 5V VIN > 5.5V, 30mA
5.0
5.5 20 10 30 200
V A mA mV
Boost FET Current Limit
TA = +25C TA = -40C, +85C
2.3 2.2 130
3.2
A A
rDS(ON)
Internal Boost Switch ON-Resistance
260
m
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ISL97636A
Electrical Specifications
All specifications below are tested at TA = -40C to +85C; VIN = 12V, EN = 5V, RSET = 36.6k; Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested (Continued) DESCRIPTION Peak Efficiency CONDITION VIN = 18V, 54 LEDs, 20mA each, L = 8.2H with DCR 106m, TA = +25C VIN = 12V, 54 LEDs, 20mA each, L = 8.2H with DCR 106m, TA = +25C VIN = 6V, 54 LEDs, 20mA each, L = 8.2H with DCR 106m, TA = +25C IOUT/VIN Dmax Dmin fS ILX_leakage REFERENCE Imatch IACC FAULT DETECTION VSC Vtemp_acc VOVPlo OVPhys OVPfault Short Circuit Threshold Over-Temperature Threshold Accuracy Overvoltage Limit on OVP Pin OVP Hysteresis OVP Short Detection Fault Level 1.17 PWM Dimming = 100% 7.8 8 5 1.2 20 300 1.23 8.8 V C V mV mV Channel-to-Channel Current Matching Current Accuracy IOUT = 30mA -3.5 1 3 +3.5 % % Line Regulation Boost Maximum Duty Cycle Boost Minimum Duty Cycle Switching Frequency LX Leakage Current VLX = 36V, EN = 0 1.0 82 7 1.2 1.3 10 MIN TYP 91 MAX UNIT %
PARAMETER Eff_peak
88
%
86
%
0.1
% % % MHz A
CURRENT SOURCES Vheadroom VRSET ILEDmax FAULT PIN Ifault Vfault IlxStartup Fault Pull-down Current VIN = 12V 10 18 7.5 1 2.7 7 30 A V mA Dominant Channel Current Source Headroom at IIN Pin Voltage at RSET Pin Maximum LED Current Per Channel ILED = 20mA TA = +25C RSET = 36.6k RSET = 20.9k 680 100 700 35 720 mV mV mA
FAULT Clamp Voltage with Respect to VIN VIN = 12, VIN - Vfault LX Start-up Current VDC = 5.2V
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ISL97636A Typical Performance Curves
92 90 88 86 82 80 78 76 74 72 70 68 66 0 20 40 60 80 IO (mA) 100 120 140 9S6P - 6V L = 8.2H IHLP-2525BD-01 DCR = 106m ISAT = 3A 7S6P - 6V 7S6P - 18V 7S6P - 12V 9S6P - 12V 9S6P - 18V EFFICIENCY (%) EFFICIENCY (%) 84 92 90 88 86 84 82 80 78 76 74 72 70 68 66 0 7S6P - 6V L = 10H IHLP-2525BD-01 DCR = 129m ISAT = 2.5A 20 40 60 80 IO (mA) 100 120 140 7S6P - 18V 9S6P - 18V 9S6P - 6V 9S6P - 12V 7S6P - 12V
FIGURE 2. EFFICIENCY, L = 8.2H WITH DCR = 106m, CO = 4x4.7F/50V
FIGURE 3. EFFICIENCY, L = 10H WITH DCR = 129m, CO = 4x4.7F/50V
92 L = 10H DCR ~ 500m 88 <1mm HEIGHT 90 86 84 82 80 78 76 74 72 70 68 66 0 20 40 60 80 IO (mA) 100 120 140 7S6P - 6V 9S6P - 6V 7S6P - 18V 7S6P - 12V 9S6P - 12V CURRENT VARIATION (%) EFFICIENCY (%) 9S6P - 18V
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 4 6 8 10 12 14 16 VIN (V) 18 20 22 24 26 20mA
FIGURE 4. 3 EFFICIENCY, L = 10H WITH DCR = 500m, 1mm, CO = 4x4.7F/50V
FIGURE 5. CURRENT REGULATION
0.020 6P9S = 54 LEDs 0.015 CURRENT MATCHING 0.010 0.005 0 -0.005 -0.010 -0.015 -0.020 6V/1mA 6V/20mA 12V/20mA CURRENT MATCHING (%) 12V/1mA
1.0 VIN = 12V 0.9 20kHz 0.8
0.7 200Hz 0.6 10kHz 1kHz 100Hz
Ch 0
Ch 1
Ch 2 Ch 3 CHANNELS
Ch 4
Ch 5
0.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 PWM DUTY CYCLE
FIGURE 6. CHANNEL-TO-CHANNEL CURRENT MATCHING
FIGURE 7. CURRENT MATCHING vs DUTY CYCLE vs DIMMING FREQUENCY
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ISL97636A Typical Performance Curves (Continued)
180 160 TOTAL OUTPUT CURRENT (mA) 140 120 VIN = 6V 100 80 60 40 20 0 0 10 20 30 40 50 60 70 PWM DUTY CYCLE% 80 90 100 VIN = 18V 6 CHANNELS 9 LEDs PER CHANNEL VIN = 12V
FIGURE 8. PWM DIMMING LINEARITY
FIGURE 9. LX, VIIN, IL AND IO AT PWM DIMMING (54 LEDs, 20mA, VIN = 12V)
FIGURE 10. IL AT 50% PWM DIMMING (54LEDs, 20mA, VIN = 12V, L = 8.2H)
FIGURE 11. IL ZOOM IN AT PWM DIMMING ZOOM IN (54 LEDs, 20mA, VIN = 12V, L = 8.2H)
FIGURE 12. ILED AT 50% PWM DIMMING (54 LEDs, 20mA, VIN = 12V)
FIGURE 13. LX AT 50% PWM DIMMING (54 LEDs, 20mA, VIN = 12V)
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ISL97636A Typical Performance Curves (Continued)
FIGURE 14. LX ZOOM IN AT 50% DIMMING (54 LEDs, 20mA, VIN = 12V)
FIGURE 15. RIPPLE VOLTAGE (54 LEDs, VIN = 12V, 20mA EACH, COUT = 4x4.7F/50V)
FIGURE 16. RIPPLE VOLTAGE ZOOM IN (54 LEDs, VIN = 12V, 20mA EACH, COUT = 4x4.7F/50V)
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ISL97636A Pinout
ISL97636A (24 LD QFN) TOP VIEW
FAULT COMP VDC VIN LX 20 LX 19 18 17 16 15 14 13 7 NC 8 NC 9 IIN5 10 IIN4 11 RSET 12 IIN3 PGND PGND OVP IIN0 IIN1 IIN2
24 GND GND FPWM VLEVEL GND PWMI/EN 1 2 3 4 5 6
23
22
21
Pin Descriptions (I = Input, O = Output, S = Supply)
PIN 1 2 3 4 5 6 7, 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME GND GND FPWM VLEVEL GND EN/PWMI NC IIN5 IIN4 RSET IIN3 IIN2 IIN1 IIN0 OVP PGND PGND LX LX FAULT COMP VIN VDC TYPE S S S I I I I I I I I I S S I I O O S S Analog GND Analog GND Not used. Leave floating and connect anything will have no effect on operation Not used. Leave floating and connect anything will have no effect on operation Analog GND and LED power return Dual Functions: Enable Pin and PWM brightness control pin. DO NOT leave EN/PWMI floating. The device needs 40s for initial power-up Enable, then this pin can be applied with a PWM signal with off time no longer than 28ms. No Connect. Can be floating or grounded Input 5 to current source, FB, and monitoring Input 4 to current source, FB, and monitoring Resistor connection for setting LED current, (see Equation 1 for calculating the ILEDpeak) Input 3 to current source, FB, and monitoring Input 2 to current source, FB, and monitoring Input 1 to current source, FB, and monitoring Input 0 to current source, FB, and monitoring Overvoltage protection input Power ground (LX Power return) Power ground (LX Power return) Input to boost switch Input to boost switch Fault disconnect switch Boost compensation pin Input voltage for the device and LED power De-couple capacitor for internally generated supply rail. If 2.7V < VBL+ < 5.5V, apply VDC directly with a supply voltage of 2.7V to 5.5V DESCRIPTION
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ISL97636A Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the minimal voltage needed to enable the LED stack with the highest forward voltage drop to run at the programmed current. The ISL97636A employes current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. Such architecture achieves a fast transient response that is essential for the notebook backlight application where the power can be a series of drained batteries or instantly changed to an AC/DC adapter without rendering a noticeable visual nuisance. The number of LEDs that can be driven by ISL97636A depends on the type of LED chosen in the application. The ISL97636A is capable of boosting up to 34.5V and typically driving 9 LEDs in series for each of the 6 channels, enabling a total of 54 pieces of the 3.5V/30mA type of LEDs.
+ RSET
+ REF
+ PWM DIMMING
FIGURE 17. SIMPLIFIED CURRENT SOURCE CIRCUIT
Enable and PWMI
The EN/PWMI pin serves dual purposes; it is used as an enable signal and can be used for PWM input signal for dimming. If a PWM signal is applied to this pin, the first pulse of minimum 40s will be used as an Enable signal. If there is no signal for longer than 28ms, the device will enter shutdown. The EN/PWMI pin cannot be floating, thus a 10k pull-down resistor may need to be added.
Dynamic Headroom Control
The ISL97636A features a proprietary Dynamic Headroom Control circuit that detects the highest forward voltage string or effectively the lowest voltage from any of the IIN pins. When this lowest IIN voltage is lower than the short circuit threshold, VSC, such voltage will be used as the feedback signal for the boost regulator. The boost makes the output to the correct level such that the lowest IIN pin is at the target headroom voltage. Since all LED stacks are connected to the same output voltage, the other IIN pins will have a higher voltage, but the regulated current source circuit on each channel will ensure that each channel has the same current. The output voltage will regulate cycle by cycle and it is always referenced to the highest forward voltage string in the architecture.
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the current source circuit, as shown in Figure 17. The LED peak current is set by translating the RSET current to the output with a scaling factor of 733/RSET. The source terminals of the current source MOSFETs are designed as 100mV to minimize the power loss. The sources of errors of the channel-to-channel current matching come from the op amp's offset, internal layout and reference and these parameters are optimized for current matching and absolute current accuracy. The absolute accuracy is also determined by the external RSET, and therefore a 1% tolerance resistor should be used.
Dimming Controls
The ISL97636A allows two ways of controlling the LED current, and therefore, the brightness. They are: 1. DC current adjustment 2. PWM chopping of the LED current defined in Step 1. MAXIMUM DC CURRENT SETTING The initial brightness should be set by choosing an appropriate value for RSET. This should be chosen to fix the maximum possible LED current:
733 I LEDmax = -------------R SET (EQ. 1)
DC CURRENT ADJUSTMENT RSET can be a DCP (Digitally Controlled Potentiometer) for DC current adjustment but minimum resistance should not be lower than 21k for a maximum of 35mA.
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ISL97636A
For example, if the maximum required LED current (ILED(max)) is 20mA, rearranging Equation 1 yields Equation 3:
R SET = 733 0.02 = 36.6k (EQ. 2)
prevents high input current for systems that have only a low to medium output current requirement. For systems with no master fault protection FET, the inrush current will flow towards COUT when VIN is applied and it is determined by the ramp rate of VIN and the values of COUT and L.
PWM CURRENT CONTROL The average LED current of each channel can be controlled by an external PWMI signal as shown in Equation 3:
I LED ( ave ) = I LED x PWMI (EQ. 3)
Fault Protection and Monitoring
The ISL97636A features extensive protection functions to cover all the perceivable failure conditions. The failure mode of a LED can be either open circuit or as a short. The behavior of an open circuited LED can additionally take the form of either infinite resistance or, for some LEDs, a zener diode, which is integrated into the device in parallel with the now opened LED. For basic LEDs (which do not have built-in zener diodes), an open circuit failure of an LED will only result in the loss of one channel of LEDs without affecting other channels. Similarly, a short circuit condition on a channel that results in that channel being turned off does not affect other channels unless a similar fault is occurring. Due to the lag in boost response to any load change at its output, certain transient events (such as LED current steps or significant step changes in LED duty cycle) can transiently look like LED fault modes. The ISL97636A uses feedback from the LEDs to determine when it is in a stable operating region and prevents apparent faults during these transient events from allowing any of the LED stacks to fault out. See Table 1 for more details. A fault condition that results in an input current that exceeds the devices electrical limits will result in a shutdown of all output channels.
The PWM dimming frequency can be, for example, 20kHz, but there are a minimum on and off time requirements such that the dimming will be in the range of 10% to 99.5%. If the dimming frequency is below 5kHz, the dimming range can be 1% to 99.5%. The PWM dimming off time cannot be longer than 28ms or else the driver will enter shutdown.
5V Low Dropout Regulator
A 5.2V LDO regulator is present at the VDC pin to develop the necessary low voltage supply which is used by the chips internal control circuitry. Because VDC is an LDO pin, it requires a bypass capacitor of 1F or more for the regulation. For applications with an input voltage 5.5V, the VIN and VDC pins can be connected together. The VDC pin can be used as a coarse reference with few mA sourcing capability.
Inrush Control and Soft-start
The ISL97636A has separately built-in independent inrush control and soft-start functions. The inrush control function is built around the short circuit protection FET, and is only available in applications, which include this device. At startup, the fault protection FET is turned on slowly due to a 30A pull-down current output from the FAULT pin. This discharges the fault FET's gate-source capacitance, turning on the FET in a controlled fashion. As this happens, the output capacitor is charged slowly through the weakly turned on FET before it becomes fully enhanced. This results in a low inrush current. This current can be further reduced by adding a capacitor (in the 1nF to 5nF range) across the gate source terminals of the FET. Once the chip detects that the fault protection FET is turned on hard, it is assumed that inrush is complete. At this point, the boost regulator will begin to switch and the current in the inductor will ramp-up. The current in the boost power switch is monitored and the switching terminated in any cycle where the current exceeds the current limit. The ISL97636A includes a soft-start feature where this current limit starts at a low value (375mA). This is stepped up to the final 3A current limit in seven further steps of 375mA. These steps will happen over a 1ms total time, such that after 1ms the final limit will be reached. This allows the output capacitor to be charged to the required value at a low current limit and
Short Circuit Protection (SCP)
The short circuit detection circuit monitors the voltage on each channel and disables faulty channels which are detected above 8V (the action taken is described in Table 1.)
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can behave as either an infinite resistance or a gradually increasing finite resistance. The ISL97636A monitors the current in each channel such that any string which reaches at least 75% of the intended output current is considered "good". Should the current subsequently fall below 50% of the target the channel will be considered an "open circuit". Furthermore, should the boost output of the ISL97636A reach the OVP limit or should the lower over-temperature threshold be reached, all channels which are not "good" will immediately be considered as "open circuit". Detection of an "open circuit" channel will result in a time-out before disabling of the affected channel. This time-out is sped up when the device is above the lower over-temperature threshold in an attempt to prevent the upper over-temperature trip point from being reached.
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ISL97636A
Some users employ some special types of LEDs that have zener diode structure in parallel with the LED for ESD enhancement and enabling open circuit operation. When this type of LED is open circuited, the effect is as if the LED forward voltage has increased but no lighting. Any affected string will not be disabled, unless the failure results in the boost OVP limit being reached, allowing all other LEDs in the string to remain functional. Care should be taken in this case that the boost OVP limit and SCP limit are set properly, so as to make sure that multiple failures on one string do not cause all other good channels to be faulted out. This is due to the increased forward voltage of the faulty channel making all other channels look as if they have LED shorts. See Table 1 for details regarding responses to fault conditions. off. This monitoring happens on a cycle-by-cycle basis in a self protecting way. Additionally, the ISL97636A monitors the voltage at the LX and OVP pins. At start-up, a fixed current is injected out of the LX pins and into the output capacitor. The device will not start-up unless the voltage at LX exceeds 1.2V. Furthermore, should the voltage at LX not rise above this threshold during any subsequent period where the power FET is not switched on, it will immediately disable the input protection FET. The OVP pin is also monitored such that if it rises above and subsequently falls below 20% of the target OVP level, the input protection FET will also be switched off.
Over-Temperature Protection (OTP)
The ISL97636A includes two over-temperature thresholds. The lower threshold is set to +130C. When this threshold is reached, any channel which is outputting current at a level significantly below the regulation target will be treated as "open circuit" and disabled after a time-out period. This time-out period is also reduced to 800s when it is above the lower threshold. The intention of the lower threshold is to allow bad channels to be isolated and disabled before they cause enough power dissipation (as a result of other channels having large voltages across them) to hit the upper temperature threshold. The upper threshold is set to +150C. Each time this is reached, the boost will stop switching and the output current sources will be switched off. Once the device has cooled to approximately +100C, the device will restart with the DC LED current level reduced to 77% of the initial setting. If the dissipation problem persists, subsequent hitting of the limit will cause identical behavior, with the current reduced in steps to 53% and finally 30%. Unless disabled via the EN pin, the device stays in an active state throughout. For the extensive fault protection conditions, please refer to Figure 18 and Table 1 for details.
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage and keeps the voltage at a safe level. The OVP threshold is set as:
OVP = 1.21V x ( R UPPER + R LOWER ) R LOWER (EQ. 4)
These resistors should be large to minimize the power loss. For example, a 1M RUPPER and 39k RLOWER sets OVP to 32.2V. Large OVP resistors also allow COUT discharges slowly during the PWM off time.
Undervoltage Lockout
If the input voltage falls below the UVLO level of 2.45V, the device will stop switching and reset. Operation will restart when the voltage comes back into the operating range.
Input Overcurrent Protection
During normal switching operation, the current through the internal boost power FET is monitored. If the current exceeds the current limit, the internal switch will be turned
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VIN LX VOUT
FAULT DRIVER
LX O/P SHORT OVP
IMAX
ILIMIT
LOGIC
FET DRIVER
VSC
IIN0
IIN5
THRM SHDN
REF T2 TEMP SENSOR T1
OTP FAULT DETECT LOGIC
VSET
Q0 VSET
Q5
PWM/OC0/SC0 PWM GENERATOR
PWM/OC5/SC5
FIGURE 18. SIMPLIFIED FAULT PROTECTIONS TABLE 1. PROTECTIONS TABLE CASE 1 FAILURE MODE CH0 Short Circuit DETECTION MODE FAILED CHANNEL ACTION GOOD CHANNELS ACTION CH1 through CH5 Normal VOUT REGULATED BY Highest VF of CH1 through CH5
CH0 ON and burns power Upper Over-Temperature Protection limit (OTP) not triggered and VIIN0 < VSC CH0 goes off until chip cooled and Upper OTP triggered but VIN0 then comes back on with current reduced to 76%. Further OTP < VSC triggers result in reduction to 53%, then 30%. Upper OTP not triggered but VIIN0 > VSC Upper OTP not triggered and VIIN0 < VSC Upper OTP not triggered and VIIN0 < VSC
2
CH0 Short Circuit
Same as CH0
Highest VF of CH1 through CH5
3
CH0 Short Circuit
CH1 through CH5 Normal CH0 doubled after 6ms time-out. Time-out reduced to 420s if above lower OTP limit VOUT will ramp to OVP. CH0 will time-out after 6ms (800s if above lower OTP limit) and switch off. VOUT will drop to normal level. CH0 remains ON and has highest VF, thus VOUT increases CH1 through CH5 Normal
Highest VF of CH1 through CH5 Highest VF of CH1 through CH5
4
CH0 Open Circuit with infinite resistance CH0 LED Open Circuit but has paralleled Zener
5
CH1 through CH5 ON, Q1 through Q5 burn power
VF of CH0
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TABLE 1. PROTECTIONS TABLE (Continued) CASE 6 FAILURE MODE CH0 LED Open Circuit but has paralleled Zener DETECTION MODE Upper OTP triggered but VIIN0 < VSC FAILED CHANNEL ACTION CH0 goes off until chip cooled and then comes back on with current reduced to 76%. Further OTP triggers result in reduction to 53%, then 30%. CH0 OFF GOOD CHANNELS ACTION Same as CH0 VOUT REGULATED BY VF of CH0
7
CH0 LED Open Circuit but has paralleled Zener
Upper OTP not triggered but VIIN0 > VSC
CH1 through CH5 Normal
Highest VF of CH1 through CH5
CH0 remains ON and has highest Upper OTP not triggered but VIINx VF, thus VOUT increases. > VSC
VF of CH0 VOUT increases then CH-X switches OFF. This is an unwanted shut off and the effect can be minimized by setting OVP at an appropriate level. Highest VF of CH0 through CH5
8
Any channel at below 50% of the target current will fault out after 400s. Channel-to-Channel Lower OTP VF too high triggered but VIINx Remaining channels driven with normal current. < VSC
9
All channels switched off until chip cooled and then comes back on with Highest VF of CH0 Channel-to-Channel Upper OTP VF too high triggered but VIINx current reduced to 76%. Further OTP triggers result in reduction to 53%, through CH5 then 30%. < VSC Output LED stack voltage too high VOUT > VOVP Driven with normal current. Any channel that is below 50% of the target current will time-out after 6ms. Fault switch disabled and system shutdown until fault goes away, VOUT is checked at start-up with a low current from LX to check for presence of short before the fault switch is enabled. Highest VF of CH0 through CH5
10 11
VOUT/LX shorted to LX current and GND timing are monitored. OVP pin monitored for excursions below 20% of OVP threshold
Components Selections
According to the inductor Voltage-Second Balance principle, the change of inductor current during the switching regulator On time is equal to the change of inductor current during the switching regulator Off time. Since the voltage across an inductor is:
V L = L x I L t (EQ. 5)
Input Capacitor
Switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. This reduces interaction between the regulator and input supply, improving system stability. The high switching frequency of the loop causes almost all ripple current to flow in the input capacitor, which must be rated accordingly. A capacitor with low internal series resistance should be chosen to minimize heating effects and improve system efficiency, such as X5R or X7R ceramic capacitors, which offer small size and a lower value of temperature and voltage coefficient compared to other ceramic capacitors. In boost mode, input current flows continuously into the inductor, with an AC ripple component proportional to the rate of inductor charging only and smaller value input capacitors may be used. It is recommended that an input capacitor of at least 10F be used. Ensure the voltage rating of the input capacitor is suitable to handle the full supply range.
and IL @ On = IL @ Off, therefore:
( V I - 0 ) L x D x tS = ( VO - VD - VI ) L x ( 1 - D ) x tS (EQ. 6)
where D is the switching duty cycle defined by the turn-on time over the switching period. VD is Schottky diode forward voltage that can be neglected for approximation. Rearranging the terms without accounting for VD gives the boost ratio and duty cycle respectively as:
VO VI = 1 ( 1 - D ) D = ( VO - VI ) VO (EQ. 7)
(EQ. 8)
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ISL97636A
Inductor
The selection of the inductor should be based on its maximum current (ISAT) characteristics, power dissipation (DCR), EMI susceptibility (shielded vs unshielded), and size. Inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance and stability. Its maximum current capability must be adequate to handle the peak current at the worst case condition. If an inductor core is chosen with too low a current rating, saturation in the core will cause the effective inductor value to fall, leading to an increase in peak to average current level, poor efficiency and overheating in the core. The series resistance, DCR, within the inductor causes conduction loss and heat dissipation. A shielded inductor is usually more suitable for EMI susceptible applications, such as LED backlighting. The peak current can be derived from the fact that the voltage across the inductor during the Off period can be shown as:
IL peak = ( V O x I O ) ( 85% x V I ) + 1 2 [ V I x ( V O - V I ) ( L x V O x f S ) ] (EQ. 9)
backlight applications due to their cost, form factor, and low ESR. A larger output capacitor will also ease the driver response during PWM dimming Off period due to the longer sample and hold effect of the output drooping. The driver does not need to boost harder in the next On period that minimizes transient current. The output capacitor is also needed for compensation, and in general, 2x4.7F/50V ceramic capacitors are suitable for the notebook display backlight applications.
Schottky Diode
A high speed rectifier diode is necessary to prevent excessive voltage overshoot, especially in the boost configuration. Low forward voltage and reverse leakage current will minimize losses, making Schottky diodes the preferred choice. Although the Schottky diode turns on only during the boost switch Off period, it carries the same peak current as the inductor's, and therefore, a suitable current rated Schottky diode must be used.
Applications
High Current Applications
Each channel of the ISL97636A can support up to 35mA. For applications that need higher current, multiple channels can be grouped to achieve the desirable current. For example, the cathode of the last LED can be connected to IIN0 to IIN2; this configuration can be treated as a single string with 105mA current driving capability.
VOUT
The choice of 85% is just an average term for the efficiency approximation. The first term is average current that is inversely proportional to the input voltage. The second term is inductor current change that is inversely proportional to L and fS. As a result, for a given switching frequency and minimum input voltage the system operates, the inductor ISAT must be chosen carefully. At a given inductor size, usually the larger the inductance, the higher the series resistance because of the extra winding of the coil. Thus, the higher the inductance, the lower the peak current capability. The ISL97636A current limit may also have to be taken into account.
Output Capacitors
The output capacitor acts to smooth the output voltage and supplies load current directly during the conduction phase of the power switch. Output ripple voltage consists of the discharge of the output capacitor for ILPEAK during FET On and the voltage drop due to flowing through the ESR of the output capacitor. The ripple voltage can be shown as:
V CO = ( I O C O x D f S ) + ( ( I O x ESR ) (EQ. 10)
IIN0 IIN1 IIN2
FIGURE 19. GROUPING MULTIPLE CHANNELS FOR HIGH CURRENT APPLICATIONS
The conservation of charge principle in Equation 8 also brings up a fact that during the boost switch Off period, the output capacitor is charged with the inductor ripple current minus a relatively small output current in boost topology. As a result, the user needs to select an output capacitor with low ESD and with a enough input ripple current capability.
Compensation
The ISL97636A has two main elements in the system; the Current Mode Boost Regulator and the op amp based multi-channel current sources. The ISL97636A incorporates a transconductance amplifier in its feedback path to allow the user some levels of adjustment on the transient response and better regulation. The ISL97636A uses current mode control architecture, which has a fast current sense loop and a slow voltage feedback loop. The fast current feedback loop does not require any compensation. The slow voltage loop must be compensated for stable operation. The
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Output Ripple
VCo can be reduced by increasing CO or fS, or using small ESR capacitors. In general, ceramic capacitors are the best choice for output capacitors in small to medium sized LCD 15
ISL97636A
compensation network is a series Rc, Cc1 network from COMP pin to ground and an optional Cc2 capacitor connected to the COMP pin. The Rc sets the high frequency integrator gain for fast transient response and the Cc1 sets the integrator zero to ensure loop stability. For most applications, Rc is in the range of 200 to 3k and Cc1 is in the range of 27nF to 37nF. Depending upon the PCB layout, a Cc2, in range of 100nF, may be needed to create a pole to cancel the output capacitor ESR's zero effect for stability. The ISL97636A evaluation board is configured with Rc1 of 500, Cc1 of 33nF, and Cc2 of 0, which achieves stability. In the actual applications, these values may need to be tuned empirically but the recommended values are usually a good starting point.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN6566.0 May 9, 2008
VIN C1 10/25V C2 0.1/25V
4 3
Q1
1 2 5 6
L1 8.2H C4 10/25V
D1 D1 : SS15 - Vishay Schottky Diode, 5 SS15 C6 4.7/50V C7 4.7/50V
FDMA530PZ C10 33n R7 500 23 22 VIN COMP C20 R3 1M LED1 LX 18 LED2 17 16 15 14 13 OVP R4 39k LED4 LED13 LED22 LED31 LED40 LED49 LED3 LED12 LED21 LED30 LED39 LED48 LED11 LED20 LED29 LED38 LED47 LED10 LED19 LED28 LED37 LED46
24
21
FAULT
VDC
1 2 3 4 5 PWMI/EN 6
GND GND FPWM
LX 11 RSET
C11 1/10V
20
PGND PGND OVP
ISL97636A PWMO GND PWMI/EN IIN5 10 IIN4 NC NC 12 IIN3 IIN0 IIN1 IIN2
19
C12 0.1/10V
7
8
9
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LED5
LED14
LED23
LED32
LED41
LED50
U1
LED6
LED15
LED24
LED33
LED42
LED51
ISL97636A
NOTES: FOR 2 LAYERS BOARD, LAYOUT PGND (NOISY GROUND) ON TOP LAYER AND AGND (QUIET GROUND) ON BOTTOM LAYER. TIE PGND AND AGND ONLY AT ONE POINT BY DOING THIS: BRIDGE U1 PGND (PINS 18 AND 19) AND AGND (PIN 5) TO THE PACKAGE THERMAL PAD. PUT MULTIPLE VIAS ON THE THERMAL PAD THAT CONNECTS TO THE BOTTOM SIDE AGND.
R2 36.6k
LED7
LED16
LED25
LED34
LED43
LED52
LED8
LED17
LED26
LED35
LED44
LED53
LED9
LED18
LED27
LED36
LED45
LED54
FIGURE 20. TYPICAL APPLICATION CIRCUIT
ISL97636A
Package Outline Drawing
L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/06
4X 2.5 4.00 A B 19 20X 0.50 24 PIN #1 CORNER (C 0 . 25)
PIN 1 INDEX AREA
18
1
4.00
2 . 50 0 . 15
13
(4X)
0.15 12 7 0.10 M C A B 0 . 07 24X 0 . 23 + 0 . 05 4 24X 0 . 4 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 0 . 1
( 3 . 8 TYP )
C BASE PLANE
SIDE VIEW
SEATING PLANE 0.08 C
(
2 . 50 ) ( 20X 0 . 5 )
C ( 24X 0 . 25 ) ( 24X 0 . 6 )
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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FN6566.0 May 9, 2008

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